IntelliProp SAS Initiator IP Core (IPC-SS105A-HI)
Block Diagram
Overview
The IntelliProp IPC-SS105A-HI, SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host designs to connect to high throughput SAS storage devices. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization and provide an industry compliant SAS 3.0 and 6.0 Gb/s interface for host designs. As with all IntelliProp cores, the IPC-SS105A-HI core is fully verified in psuedo-random simulation. Target applications for the IPC-SS105A-HI core include: Internal interconnect for workstation and server storage; Enterprise storage interconnect; HDD/SSD hot-swap environments; SAS Emulator/test boxes.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2008 |
| Latest version of Quartus supported | 16.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | RTL Encrypted code; synthesis or place & route script |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | standalone |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim |
| Hardware validated | Y. Altera Board Name Arria V, Arria 10, Stratix IV, Stratix V |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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