IntelliProp NVMe-to-NVMe Bridge (IPC-NV171A-BR)
Block Diagram
Overview
The IntelliProp IPC-NV171A-BR, NVMe-to-NVMe Bridge utilizes the IntelliProp NVMe Host Accelerator Core and the IntelliProp NVMe Target Core to create an NVMe protocol bridge. The bridge is architected such that the command submissions, completion notifications and data transmissions may be either passed through without interruption or intercepted for analysis or modification. The architecture implements a ”sandbox” area in the bridge so that IntelliProp customers may implement their own custom RTL and/or firmware in the bridge. The protocol interface is compliant to the NVM Express 1.3 specification and is fully verified using a coverage driven methodology in pseudo random simulation. Applications include: High performance read/write caching; Data Deduplication; LBA Remapping; Namespace manipulation; Data encryption; Data compression; Endpoint aggregation.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 16.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Synthesis and place and route scripts |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | Linux |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim |
| Hardware validated | N. Altera Board Name Arria 10 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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