From IntelliProp, Inc.

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Documentation

IntelliProp NVMe Target IP Core (IPC-NV163A-DT)

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Intel® Arria® 10, Arria® V

Stratix Series: Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The IntelliProp IPC-NV163A-DT is an industry standard NVMe Target IP core that allows customers to build high speed NVMe (PCIe) storage devices. The IPC-NV163A-DT provides a hardware accelerated queue management interface for NVMe commands and completions as well as provides the NVMe controller register interface for host communication and controller management. The NVMe Target Core is available for integration into Intel FPGA designs to provide an industry compliant NVMe interface at PCIe Gen3, Gen2 or Gen1 speeds. Target applications include: • NVMe SSD Controllers • NVMe fabric devices • NVMe Bridge Systems

Features

Fully compliant to the NVM Express 1.3 industry specification
Compatible with 3rd party PCIe Endpoints
Application layer (command based) interface with Processor interfac
Processor interface for register access
Automated PCIe interrupt generation on posting of completions

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	RTL Encrypted code; simulation script; synthesis or place & route script
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	linux
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name Arria 10
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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