IntelliProp AES-XTS Encryption Core (IPC-BL120A-ZM)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The IntelliProp IPC-BL120A-ZM is an AES-XTS Encryption Core supporting 128 or 256 bit encryption. The IPC-BL120A-ZM provides encryption/decryption based on a design principle known as substitution-permutation network (SP-network). An SP-network takes a block of the plaintext (clear data or non-encrypted data) and the key as inputs, and applies several alternating “rounds” or “layers” of substitution boxes and permutation boxes to produce the ciphertext (encrypted data). The IPC-BL120A-ZM is fully verified in pseudo random simulation. Applications include: high throughput data paths requiring encryption; applications requiring high levels of encryption; applications requiring FIPS-197 certified encryption/decryption algorithms.


  • 128 or 256 bit selectable AES encryption
  • The AES-XTS algorithm is FIPS-197 certified, cert. no 2408
  • The encode and decode channels are made to look and act like independent FIFOs for ease of integration.
  • Programmable number of pipeline paths allows the user to balance area/bandwidth requirements.
  • Independent Cipher/Inverse Cipher key management

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at to discuss specific needs for your project.

IP Quality Metrics

Year IP was first released2013
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Simulation Script, Sample Vectors
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportn/a
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated N. Altera Board Name Cyclone V,
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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