IntelliProp Advanced Flash Controller Interface (AFCI) (IPC-BL157A-ZM)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The IPC-BL157-ZM, Advanced Flash Controller Interface (AFCI) is a register level interface that allows software and hardware state machines the ability to communicate with a nonvolatile memory subsystem. The command communication, data movement, and status information are accomplished with a minimal number of non-cacheable read/writes. This is important to maximize throughput and minimize impact of register read/writes to platform software. Applications for the IPC-BL157A-ZM include: Embedded applications that require communication with NAND arrays; NVDIMM applications; Solid State Disk (SSD) controllers. Optional AES-XTS 256 bit encryption is optional.•\tAny system requiring communication with persistent storage

Features

  • Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
  • Separate Administrative and I/O queues for flexible datapath management
  • Maximum of 1 register write per command submission/ completion
  • Independent R/W channels allow data movement from system to NAND and NAND to system concurrently
  • Supports ONFI 3.2 and 4.0 compliant TLC, MLC and SLC NAND

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Simulation script, sample vectors
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Arria 10
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.