The IPC-BL157-ZM, Advanced Flash Controller Interface (AFCI) is a register level interface that allows software and hardware state machines the ability to communicate with a nonvolatile memory subsystem. The command communication, data movement, and status information are accomplished with a minimal number of non-cacheable read/writes. This is important to maximize throughput and minimize impact of register read/writes to platform software. Applications for the IPC-BL157A-ZM include: Embedded applications that require communication with NAND arrays; NVDIMM applications; Solid State Disk (SSD) controllers. Optional AES-XTS 256 bit encryption is optional.â€¢\tAny system requiring communication with persistent storage
Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
Separate Administrative and I/O queues for flexible datapath management
Maximum of 1 register write per command submission/ completion
Independent R/W channels allow data movement from system to NAND and NAND to system concurrently
Supports ONFI 3.2 and 4.0 compliant TLC, MLC and SLC NAND
Device Utilization and Performance
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IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Simulation script, sample vectors
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Arria 10
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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