ECC with BCH Algorithm (IPC-BL119A-ZM)
Block Diagram

Overview
The IntelliProp IPC-BL119A-ZM is a highly configurable IP core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across noisy or unreliable communication channels. The ECC core uses the industry standard BCH class of error correcting codes. Applications for the iPC-BL119A-ZM include: Data Storage devices (SATA, SAS, FLASH); Satellite communications / telemetry; Radiowave signal recording; Wireless communications; High-speed modems such as ADSL, xDSL, etc.; Power line standards.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2015 |
Latest version of Quartus supported | 16.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Simulation Script, Sample Vectors |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | N |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | n/a |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Modelsim |
Hardware validated | Y. Altera Board Name Cyclone V, |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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