From IntelliProp, Inc.

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Documentation

ECC with BCH Algorithm (IPC-BL119A-ZM)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

The IntelliProp IPC-BL119A-ZM is a highly configurable IP core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across noisy or unreliable communication channels. The ECC core uses the industry standard BCH class of error correcting codes. Applications for the iPC-BL119A-ZM include: Data Storage devices (SATA, SAS, FLASH); Satellite communications / telemetry; Radiowave signal recording; Wireless communications; High-speed modems such as ADSL, xDSL, etc.; Power line standards.

Features

High bandwidth, low latency parallel encode and decode paths
Configurable number of encode/decode blocks
Configurable code word length (K), up to 1024 bytes
Configurable 32, 64, 128, or 256 “FIFO” data interface
User selectable error correction values (T)

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released	2015
Latest version of Quartus supported	16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Simulation Script, Sample Vectors
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	n/a
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name Cyclone V,
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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