HyperLink High Speed DSP Interface Core
Block Diagram

Overview
The Integretek HyperLink FPGA core leverages the proven TI HyperLink technology connecting your FPGA design to a Texas Instruments C66X multi-core DSP at link rates up to 25 Gb/s. The Integretek HyperLink Core allows the creation of a user defined system which can communicate with remote TI Cx66 DSP devices via a high speed SERDES interface. Developers can choose either an industry standard AXI4 bus or DMA interface. The HyperLink IP is available in both a x4 lane configuration and low cost x1 lane configuration.
Device Utilization and Performance
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | AXI; Other: DMA Master/Slave |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Mentor Questa |
Hardware validated | Y. Altera Board Name Arria 10 GX Dev Kit DK-DEV-10AX115S-A |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.