From Integre Technologies, LLC

HyperLink High Speed DSP Interface Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V

Cyclone Series: Cyclone® V

Stratix Series: Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The Integretek HyperLink FPGA core leverages the proven TI HyperLink technology connecting your FPGA design to a Texas Instruments C66X multi-core DSP at link rates up to 25 Gb/s. The Integretek HyperLink Core allows the creation of a user defined system which can communicate with remote TI Cx66 DSP devices via a high speed SERDES interface. Developers can choose either an industry standard AXI4 bus or DMA interface. The HyperLink IP is available in both a x4 lane configuration and low cost x1 lane configuration.

Features

AXI4 compliant or DMA Master/Slave interfaces
Point-to-point connection, Link self-initializes
Supports multiple outstanding read, write and interrupt transactions
Simple packet-based transfer protocol for memory mapped access
64 user defined interrupt inputs, level and pulse sensitive

Device Utilization and Performance

The HyperLink protocol supports data rates up to 25Gbps. Actual data rates will depend on available transceiver speed and hardware implementation. Available HyperLink data rates in Gbps are as follows (lane/x4): 1.25/5 Gbps 3.125/12 Gbps 6.25/25 Gbps 10/40 Gbps (pending)

Getting Started

Refer to the HyperLink High Speed DSP Interface FPGA Core User Manual for integration details.

IP Quality Metrics

Basic
Year IP was first released	2012
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	AXI; Other: DMA Master/Slave
IP-XACT Metadata included	N
Verification
Simulators supported	Mentor Questa
Hardware validated	Y. Altera Board Name Arria 10 GX Dev Kit DK-DEV-10AX115S-A
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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