High-Performance Gigabit Ethernet MAC

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

Easily integrated into Nios® II systems using Platform Designer (formerly QSYS), Avalon-MM interface for Nios II processorIndependent clock domains for Nios II and GMAC II, Royalty free, Verified on Nios II development board, Evaluation version available, Reference software included

Features

  • High Performance Gigabit Ethernet MAC, Up to 114 MByte/s UDP data
  • Easily integrated into Nios® II systems using Platform Designer (formerly Qsys), Avalon-MM interface for Nios II processor
  • Independent clock domains for Nios® II and GMAC II, configurable receive and transmit buffers
  • Jumbo frame support, MAC address and IP filter, selectable PHY interface
  • Configuration and generation by Platform Designer (formerly Qsys) and configuration GUI

Device Utilization and Performance

about 3000 LE and minimum 8 M9K for Cyclone® III and Cyclone IVabout 1500 ALM and minimum 8 M10K for Stratix® and Cyclone V

Getting Started

Contact IFI for more information

IP Quality Metrics

Basic
Year IP was first released2005
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportNIOS baremetal
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim Altera Edition
Hardware validated Y. Altera Board Name Cyclone III FPGA Development Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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