CAN_FD MegaCore Function

Block Diagram

Solution Type: IP Core

End Market: Automotive, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

Efficient CAN_FD and CAN controller. Easily integrated into Platform Designer (formerly Qsys) systems, Avalon-MM interface, Dynamic size for each message in first-in-first-out (FIFO) buffers, Software drivers shipped with intellectual property , Verified on Nios® II processor development board, Evaluation version available Software examples included

Features

  • CAN_FD and CAN 2.0B
  • Up to 64 kilobytes (KB) message transmit buffer
  • Up to 64 KB message receive buffer
  • 256 message filters

Device Utilization and Performance

about 5200 LE and minimum 5 M9K for Cyclone® III, Cyclone IV, Intel® MAX®10about 2500 ALM and minimum 5 M10K for Stratix® and Cyclone V

Getting Started

CAN 2.OB Standard or Extended Identifier, Remote Frames, Error-Handling CAN_FD 1.0 ISO 11898-1 and non-ISO, up to 64 Byte Data, Flexible Data rate, Separate Message FIFO with dynamic size for each message.Separate Clock for CAN and Avalon-MM interface possible, One High Priority Message, Bus-Statistic possible, 32 Bit Timestamp or 64 Bit.

IP Quality Metrics

Basic
Year IP was first released2013
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportNIOSII baremetal
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim Altera Edition
Hardware validated Y. Altera Board Name IXXAT CAN-IB 500/PCIe
Industry standard compliance testing performed
Y
If yes, which test(s)?ISO 16845:2004
If yes, on which Altera device(s)?Stratix II
If Yes, date performed
10/04/2013
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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