TotalHistory Embedded Logic Analyzer

Block Diagram

Solution Type: IP Core

End Market: Test & Measurement

Evaluation Method: Source Code

Technology: Basic Functions: Simulation, Debug and Verification

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

The TotalHistory IP provides an effective and simple means to probe and to debug complex FPGA designs using on-board and peripheral DDR memory banks to record signal trace at virtually infinite depth. The distinctive features of TotalHistory are its ability to work with huge memory banks and to trace multiple signals using multi-stage trace triggering conditions. Each trace port can be uniquely configured, including the port’s operating frequency, the port’s bus width, allocated trace memory size, and the port’s triggering scheme. Software controlled triggering mechanism, based on real-time signal state detection, allows for multi-stage conditional triggering to detect and to analyze unique signal conditions. Moreover, run-time control of the probes enables flexibility to change the probing configuration without a need to recompile. Trace data is offloaded via PCIe to the host computer enabling selective reconstruction of conditions of interest to efficiently resolve bugs.

Features

  • Scalable ultra-deep tracing depth (1-128 GB)
  • Utilizes unused on-board memory and unused memory bandwidth
  • Run-time control of probe ports enabling throughput and probe optimization.
  • Each probe port may work in its own clock domain and bus width
  • User-friendly interface for probe configuration

Device Utilization and Performance

Typical application requires 70 M20K block which translates to a small percent of available logic. Typical performance is 10 GB/s probe tracing in dependence of memory used.

Getting Started

The TotalHistory is seamlessly added to the user's top-level HDL design using the Gidel ProcWizard. The probe recording and triggering configuration is performed via the TotalHistory application or via the user application based on the TotalHistory API

IP Quality Metrics

Basic
Year IP was first released2012
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportWindows and Linux
Implementation
User InterfaceOther: PCIe
IP-XACT Metadata includedN
Verification
Simulators supportedN/A
Hardware validated Y. Altera Board Name All Gidel Proc boards
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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