Proc10S -Stratix 10 based High-Performance Scalable Compute Intensive Accelerator
Board Image

Block Diagram

Overview
Gidel's latest high-performance scalable compute acceleration system, the Proc10S, pushes data processing power to new heights with peak single precision performance of up to 10 TFLOPS. The Proc10S features an Intel® Stratix® 10 FPGA with up to 2.8 million logic elements, 260 GB DDR4 memory, and an option for a SoC Quad-core 64-bit ARM Cortex-A53 MPCore processor.The Proc10S boasts a 16-lane PCIe Gen. 3 host interface and 26 Gb/s and 17.4 Gb/s SERDES I/O transceivers for ultra-fast data injection to the FPGA. Abundant transceiver I/O connectivity enables a total of 400 Gb/s and includes: 2x QSFP28, 2x SFP28, and Gidel's proprietary high-speed connectors.The Proc10S offers designers huge logic resources with incredible flexibility and performance capabilities to meet the most demanding design requirements. The Proc10S can address the design challenges of virtually all end markets, including HPC, storage, broadcast, medical, and test and measurement.The Proc10S is supported by Gidel's unique proprietary tools for developing on FPGA. These tools offer a solution that is unique in the market and can be used together with Intel's design tools to achieve unmatched development efficiency and efficacy. The Gidel development tools suite includes Gidel's Developer's kit as well as OpenCL BSP and HLS (i++) ASP based on Intel's SDK.
Development Kit Hardware Contents
- PCIe x16 Gen. 3 or stand-alone, Stratix® 10 GX/SX FPGA Up to 2,800K logic elements
- For SX devices, Quad-core 64-bit ARM Cortex-A53 MPCore processor
- Up to 10× 26 Gb/s + 8x 17.4 Gb/s reconfigurable transceivers (total of 400 Gb/s)
- Form factor: Full-height, double-width, ¾ length PCI Express card, Supports up to 12V/300W
- 2x QSFP28, 2x SFP28, and Gidel high-speed connectors with Multi-level memory structure (260+ GB)
Development Kit Software Contents
- Supported by Gidel’s OpenCL BSP and HLS (I++) ASP based on Intel’s SDK
- Supported by Gidel’s Developer’s Kit: Simultaneous acceleration of multiple applications or processes, Unmatched HDL design productivity
- Simple integration with software applications with C/C++ API in Woindows and Linux
- Intel® Tools: Quartus® Prime® Pro, including Platform Designer (formerly Qsys) and DSP builder
- Generation of environment FPGA code, including all board/IP constrains and user logic wrapper
Support Document
File Name | Description | Version |
---|---|---|
doc-us-dsnbk-3-5702310901350-proc10s-datasheet.pdf | Proc10S data sheet | 1 |
Board Quality Metrics
Basic |
|
---|---|
Latest version of Quartus supported | 17.0 |
Required Collateral Available | |
User Guide | Y |
Board Schematics | N |
Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 00 |
Parts per Million (PPM) | 00 |
Board Policy | |
Return Material Authorization (RMA) Policy | Please contact Gidel |
Compliance | |
RoHS Compliant | Y |
CE Compliant | N. Only for systems |
Conflict Mineral Policy Compliant |
Y |
Test Plan Summary | |
GUI based Applications software for board diagnostics |
|
Additional Compliance | |
ISO 9000 & 9001 |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.