Stereo Vision IP Suite

Block Diagram

Solution Type: IP Core

End Market: Automotive, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

Stereo Vision is a type of distance sensor using two cameras.This technology can output the distance from these cameras to an object's surface. Stereo Vision can instantaneously detect the size, speed and position of three-dimensional objects. Stereo Vision can be applied to a wide range of applications as an advanced means of distance and object detection. FUJISOFT implements the leading Stereo Vision algorithm on Intel® FPGAs and is able to customize services to match your system specifications.

Features

  • Cyclone® V SoC Evaluation Kit containing
  • Stereo Vision IP Suite evaluation version
  • 5.0M pixel CMOS stereo camera
  • PC connection to try to stereo image viewer immediately
  • Distance detection

Device Utilization and Performance

Device Utilization for the Cyclone® V SoC implementation: LE count: 23.3K, ALMs (61.7K), RAM: 3.4 Mbit

Getting Started

Stereo Vision Evaluation Kit (http://www.fsi-embedded.jp/_emb/sv_eng/evaluationkit_eng.html)Learn more about the technology (http://www.fsi-embedded.jp/_emb/sv_eng/feature_eng.html)Learn more about the uses cases (http://www.fsi-embedded.jp/_emb/sv_eng/example_eng.html)Watch a demonstration of Stereo Vision on Intel® FPGA SoC (https://www.youtube.com/watch?list=PLZqoxJcFmJggOQpTBkWfta2x6XLDPD_qd&v=OI7CLde7njI)

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported14.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Any additional customer deliverables provided with IP
No
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedNo
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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