SDXC Host Controller IP Core
Block Diagram
Getting Started
This is a controller that manages data transfer through an SD card. This Product is embedded for use in FPGA or ASIC. SDHC memory cards adopted FAT32 as a file system. FAT32 complied with the standards but its max capacity was limited to 32GB However, the emergence of digital cameras with over 10,000 pixels and High definition (HD) video or filming functions requires larger capacity and faster transfer speeds. Therefore, SDXC standards were designed. They support 2TB at max capacity and have adopted exFAT as a file system. In order to realize faster transfers, UHS-I standards were also chosen. The transfer speed was improved from the previous maximum of 25MB/s to 104MB/s (The transfer rates above are theoretical figures). This product supports both SDXC and UHS-I.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2012 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | Nios II |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | No |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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