From FUJISOFT INCORPORATED

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Documentation

SDXC Host Controller IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Qsys Interconnect: Memory Mapped

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Overview

FUJISOFT's SDXC host controller IP is compliant with the Physical Layer Specification Version 3.0 (SDXC) and supports Ultra-High Speed (UHS-I) mode with a peak bandwidth of 104 Mbps

Features

Device Utilization and Performance

Large-Capacity: Up to 2TB Fast Transfer: Up to 104MB/s Actual measured value: Read:95.7MB/s/ White84.9MB/s (Approx. 2 to 4 times faster than USB2.0.)

Getting Started

This is a controller that manages data transfer through an SD card. This Product is embedded for use in FPGA or ASIC. SDHC memory cards adopted FAT32 as a file system. FAT32 complied with the standards but its max capacity was limited to 32GB However, the emergence of digital cameras with over 10,000 pixels and High definition (HD) video or filming functions requires larger capacity and faster transfer speeds. Therefore, SDXC standards were designed. They support 2TB at max capacity and have adopted exFAT as a file system. In order to realize faster transfers, UHS-I standards were also chosen. The transfer speed was improved from the previous maximum of 25MB/s to 104MB/s (The transfer rates above are theoretical figures). This product supports both SDXC and UHS-I.

IP Quality Metrics

Basic
Year IP was first released	2012
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	N
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	Nios II
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	No
Hardware validated	N. Altera Board Name NULL
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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