Synchronous ONFI NAND Flash Controller (EP502)
Block Diagram
Overview
The EP502 NAND Flash controller provides a simple interface for user to access SLC and MLC NAND Flash devices. The EP502 manages all the hardware protocols and allows the user to access NAND Flash memory simply by reading and writing control registers of the IP core. The EP502 supports both synchronous and asynchronous double data rate data transfer and is ONFI compliant. It provides much higher data throughput than traditional asynchronous NAND interface. Hardware generated ECC provides the required multi-bit ECC protection for NAND Flash devices. BCH code is used for multi-bit ECC up to 60 bits per 512 or 1k byte data block. Error correction can be done in hardware or software to allow different optimization between size and performance. The EP502 offers many features to improve system performance including DMA, boot ROM support, and a wide choice of user interfaces such as AHB, AXI, Avalon, PLB, wishbone and generic bus.
Features
- Supports synchronous and asynchronous NAND Flash devices with SDR and DDR data transfer
- ONFI compliant with support for non-standard NAND Flash commands
- ECC correction with BCH code for multi-bit ECC error with options for hardware or software assisted error correction
- DMA engine and boot ROM support
- Choice of AHB, AXI, Avalon, PLB, wishbone and generic user interface
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2004 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | OS independent |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | Y. Altera Board Name Custom build board |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | ONFI |
| If yes, on which Altera device(s)? | Cyclone |
| If Yes, date performed | 01/01/2004 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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