SD/SDIO 3.0 Slave Controller (EP563)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The EP563 SD 3.0 Slave Controller IP core provides the simplest way to design a Secure Digital (SD) or MultiMedia Card (MMC) device. It serves as a bridge between the SD bus and user's application logic inside the card. It contains many flexible design features that allows it to be easily integrated to any card applications. It supports SD memory, SDIO, SDHC, MMC and combo card functions.


  • Compatible with SD 3.0. Supports SD, SPI, SD Combo card, and optional 8-bit MMC bus protocol
  • USH-I Ultra High Speed up to 104Mbyte/sec and DDR mode
  • Simple 32-bit master interface to DMA data into user memory space
  • Selectable maximum block size from 512 to 16Kbytes.
  • Supports CPRM security commands and rev 3.0 extended command set

Device Utilization and Performance

3300 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: WWW:

IP Quality Metrics

Year IP was first released2004
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportOS independent
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If yes, which test(s)?SD Specification
If yes, on which Altera device(s)?Cyclone
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.