Pipeline SDRAM Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The pipeline SDRAM controller is a high-performance SDRAM controller designed for transferring data to and from any industry standard SDRAM or PC100/133 SDRAM DIMM at the highest possible data rate. It interfaces between a multiple SDRAM memory subsystem and a user interface. It performs SDRAM read and write accesses based on user requests. The pipeline feature allows the user to specify the next access address while the current data transfer is in progress. It also allows column-only access for both read and write. The SDRAM controller can be programmed to support different sizes and configurations of SDRAMs.


  • Supports industrial standard SDRAM from 64 Mbit to 256 Mbit device sizes
  • Supports both discrete SDRAM chips and PC100/133 SDRAM dual in-line memory module (DIMM)
  • Receive buffer: ring buffer, 4000 bytes
  • Designed with synthesizable hardware description language (HDL) for programmable logic device (PLD) and ASIC synthesis
  • Supports register mode and non-register mode SDRAM DIMM

Device Utilization and Performance

1057 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportOS independent
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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