Pipeline SDRAM Controller
Block Diagram
Overview
The pipeline SDRAM controller is a high-performance SDRAM controller designed for transferring data to and from any industry standard SDRAM or PC100/133 SDRAM DIMM at the highest possible data rate. It interfaces between a multiple SDRAM memory subsystem and a user interface. It performs SDRAM read and write accesses based on user requests. The pipeline feature allows the user to specify the next access address while the current data transfer is in progress. It also allows column-only access for both read and write. The SDRAM controller can be programmed to support different sizes and configurations of SDRAMs.
Features
- Supports industrial standard SDRAM from 64 Mbit to 256 Mbit device sizes
- Supports both discrete SDRAM chips and PC100/133 SDRAM dual in-line memory module (DIMM)
- Receive buffer: ring buffer, 4000 bytes
- Designed with synthesizable hardware description language (HDL) for programmable logic device (PLD) and ASIC synthesis
- Supports register mode and non-register mode SDRAM DIMM
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2000 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | OS independent |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | Y. Altera Board Name Custom build board |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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