PCI-to-PCI Bridge
Block Diagram
Segments:
Supported Device Family:
Solution Type:
Overview
The EP440 is a 32-bit PCI-to-PCI transparent bridge used for bus expansion. With the bridge IP core, the PCI bus system can be expanded virtually without limit to accommodate many PCI devices. Based on address mapping programmed to the core, the bridge selectively forwards transactions across the primary and secondary buses while keeping local transactions local to minimize bandwidth consumption. The bridge is capable of configuring all the secondary bus devices. The bridge has dual write buffer in each direction to handle simultaneous transactions on both the primary and secondary bus. Read transactions across the bridge are handled as delay read according to the PCI bridge specification. All different types of transfer termination and exceptions are handled by the core and all transaction ordering rules are observed strictly by the PCI bridge core. It is a transparent bridge so software alternation is not required. Multiple PCI bus segments can be built with several PCI bridges.
Features
- Pipeline access allows continuous data transfer without wasted cycle
- Designed for programmable logic device (PLD) and ASIC implementation in various systems environments
- Fully static design with edge-triggered flip-flops
- Independent asynchronous PCI clocks on primary and secondary bus
- Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2000 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | All PCI Compatible |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PCI Compliance |
| If yes, on which Altera device(s)? | Flex10K |
| If Yes, date performed | 01/01/1997 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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