PCI-to-PCI Bridge

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The EP440 is a 32-bit PCI-to-PCI transparent bridge used for bus expansion. With the bridge IP core, the PCI bus system can be expanded virtually without limit to accommodate many PCI devices. Based on address mapping programmed to the core, the bridge selectively forwards transactions across the primary and secondary buses while keeping local transactions local to minimize bandwidth consumption. The bridge is capable of configuring all the secondary bus devices. The bridge has dual write buffer in each direction to handle simultaneous transactions on both the primary and secondary bus. Read transactions across the bridge are handled as delay read according to the PCI bridge specification. All different types of transfer termination and exceptions are handled by the core and all transaction ordering rules are observed strictly by the PCI bridge core. It is a transparent bridge so software alternation is not required. Multiple PCI bus segments can be built with several PCI bridges.


  • Pipeline access allows continuous data transfer without wasted cycle
  • Designed for programmable logic device (PLD) and ASIC implementation in various systems environments
  • Fully static design with edge-triggered flip-flops
  • Independent asynchronous PCI clocks on primary and secondary bus
  • Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1

Device Utilization and Performance

4420 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportAll PCI Compatible
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If yes, which test(s)?PCI Compliance
If yes, on which Altera device(s)?Flex10K
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

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