PCI Bus Arbiter
Block Diagram
Segments:
Supported Device Family:
Solution Type:
Overview
The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master. The PCI bus arbiter implements either rotating priority or a fixed priority scheme. In the rotating priority scheme, the requestor that is most recently granted the bus receives the lowest priority, while the requestor position next to it receives the highest priority. The remaining requestor receives subsequently lower priority based on its position. This megafunction is available in Intel® hardware description language, Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize the design according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2000 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | All PCI compatible |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PCI Compliance |
| If yes, on which Altera device(s)? | Flex10K |
| If Yes, date performed | 01/01/1997 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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