NAND Flash Controller (EP501)
Block Diagram
Overview
The EP501 NAND Flash controller provides an easy interface for user to access NAND Flash devices. NAND Flash devices, with its unique protocol of command, address, data cycles and ECC requirements, requires extra design effort and this IP core solves this problem and makes NAND Flash devices user-friendly again. The EP501 NAND Flash controller supports BCH code for multi-bit error correction with option for hamming code single-bit error correction. Up to 60-bit ECC capability can be provided. Multiple NAND Flash devices can be cascaded to provide large memory space while the 16-bit data width option double the data bandwidth. Multi-channel design can also be realized with multiple core instantiation. While ONFI compliant, the EP501 also includes many features to improve system performances such as DMA, boot ROM support, write-trigger-read and a large choice of CPU bus interface options.
Features
- ECC correction with BCH code for up to 60-bit ECC error per 512 or 1k byte of data blocks
- Programmable support for different page and spare column sizes
- Supports single-level and multi-level cells (SLC and MLC) asynchronous NAND Flash devices
- ONFI NAND compliant with support for non-standard commands
- Optional built-in DMA and boot ROM support
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2000 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | OS independent |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | Y. Altera Board Name Custom build board |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | ONFI |
| If yes, on which Altera device(s)? | Cyclone |
| If Yes, date performed | 01/01/2004 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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