NAND Flash Controller (EP501)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The EP501 NAND Flash controller provides an easy interface for user to access NAND Flash devices. NAND Flash devices, with its unique protocol of command, address, data cycles and ECC requirements, requires extra design effort and this IP core solves this problem and makes NAND Flash devices user-friendly again. The EP501 NAND Flash controller supports BCH code for multi-bit error correction with option for hamming code single-bit error correction. Up to 60-bit ECC capability can be provided. Multiple NAND Flash devices can be cascaded to provide large memory space while the 16-bit data width option double the data bandwidth. Multi-channel design can also be realized with multiple core instantiation. While ONFI compliant, the EP501 also includes many features to improve system performances such as DMA, boot ROM support, write-trigger-read and a large choice of CPU bus interface options.


  • ECC correction with BCH code for up to 60-bit ECC error per 512 or 1k byte of data blocks
  • Programmable support for different page and spare column sizes
  • Supports single-level and multi-level cells (SLC and MLC) asynchronous NAND Flash devices
  • ONFI NAND compliant with support for non-standard commands
  • Optional built-in DMA and boot ROM support

Device Utilization and Performance

1000 LE, 100 MHz

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: WWW:

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportOS independent
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If yes, which test(s)?ONFI
If yes, on which Altera device(s)?Cyclone
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

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