DMA Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Basic Functions: DMA

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The DMA controller is designed for data transfer in different system environments. Two module types : type 0 and type 1 are provided, and the user can choose the number of each module type. Type 0 modules are designed to transfer data residing on the same bus, and Type 1 modules are designed to transfer data between two different buses. Each module can support up to 4 DMA channels and the IP supports up to 16 total DMA channels. Each DMA channel can be programmed for various features, such as transfer size, synchronized and unsynchronized transfer control, transfer priority, interrupt generation, memory and I/O address space, and address change direction. This IP is designed to work with 32-bit and 64-bit bus systems, including the PCI bus, PowerPC bus, and other CPU host buses. It can also be integrated with other IP to form a complete functional block.


  • Supports both synchronous and asynchronous DMA transfers
  • Designed for peripheral component interconnect (PCI) and other central processing unit (CPU) bus systems
  • General-purpose direct-memory access (DMA) controller
  • Up to 16 DMA channels

Device Utilization and Performance

2300 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: WWW:

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportOS independent
User InterfaceAXI; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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