DMA Controller for AHB

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Basic Functions: DMA

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The EP246 DMA controller is designed to operate directly on the AHB. It contains multiple channels that can be programmed independently. Each channel has dedicated interface to IO ports and channels can arbitrates for the command AHB bus interface. DMA can be started either by a hardwire input signal or under software control. It implements scatter gather DMA chaining. At the end of the DMA transfer, the controller automatically loads a new set of DMA. User can set up many different DMA transfers by providing a link list in memory and have the controller execute each DMA transfer sequentially. Scatter gather is useful for merging data from different data locations into one contiguous location. Misaligned data transfer is also support. In this case, source and destination data does not lineup at the same word boundary and the IP core realigns the data during transfer. Interrupt is also supported.


  • Supports both hardware initiated transfer and software initiated transfer
  • Dedicated read buffer with data width matching
  • DMA transfers between AHB memory devices and I/O ports
  • Scatter-gather allows DMA to merge multiple data source to contiguous space
  • Multiple independent DMA channels with direct advanced high-performance bus (AHB) interface

Device Utilization and Performance

1818 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: WWW:

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportOS independent
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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