AHB to SDRAM Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The AHB bus SDRAM controller provides high speed SDRAM access for the system. It features one AHB port for user to access SDRAM. It is also available in multipe port configuration for memory sharing. All the access port can be AHB or a mixture of other bus interface. A generic user interface can be provided for optimal system core logic or DMA access. The SDRAM controller contains built-in arbitration unit in the case of multiple port setup to allow both the AHB CPU and other system core logic to share SDRAM access. Sophisticated priority scheme allows data sharing to be customized to application requirements.

Features

  • SDRAM controller interfaces directly with advanced high-performance bus (AHB) and user interface
  • Built-in arbitration between two access ports
  • Dual write buffer for simultaneous write posting and SDRAM access
  • Second access port allows memory sharing with user logic devices

Device Utilization and Performance

2646 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Basic
Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportOS independent
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Verification
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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