64-Bit PCI Master/Target Interface
Block Diagram
Overview
The 64-bit PCI master/target megafunction interfaces bus mastering devices, such as direct-memory access (DMA) controllers or video coprocessors, to the PCI bus. It processes all data requests from the bus mastering device and translates them into PCI bus requests. This megafunction is designed for a 64-bit PCI bus system, which doubles the data bandwidth of a 32-bit PCI system. It supports zero-wait state burst transfers and a very long burst length. The megafunction supports up to a 266 Mbytes per second data transfer rate, and both 64-bit and 32-bit data transfers. The 64-bit PCI master/target megafunction contains the functions of a bus master and a bus target. The device data and status can be accessed as a PCI master or target. All compliant configuration registers are included in the megafunction and all configuration accesses are processed automatically. This megafunction is available in Intel® Hardware Description Language, Verilog HDL, VHDL, and netlist format.
Features
- Maps PCI address space to ISA address space through a base address register
- Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
- 64-bit PCI bus
- Zero-wait state burst data transfer
- Includes both bus master and bus target functions
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | All PCI compatible |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PCI Compliance |
| If yes, on which Altera device(s)? | Flex10K |
| If Yes, date performed | 01/01/1997 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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