The 64-bit PCI host bridge is designed for interfacing the host CPU with the PCI bus. The host bridge consists of three functions: bus master, bus target, and configuration access generation. A highly efficient and flexible backend bus interfaces with the system CPU and user defined logic, such as direct memory access (DMA) and memory controllers. The core utilizes the double data buffer design approach that minimizes design gate count and achieves the highest possible data bandwidth at the same time. The host bridge core allows the central processing unit (CPU) or user logic to initialize the entire system during power-up reset. Configuration Mechanism #1, as defined by the PCI specification, is implemented by the host bridge, and both type zero and type one transactions are supported. This megafunction is available in Intel® hardware description language, Verilog, VHDL, and netlist format. Sizes vary with features and customization. Eureka Technology can customize.