64-Bit PCI Bus Target Interface

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The 64-bit PCI target megafunction is designed for interfacing user logic with a 64-bit PCI bus. This megafunction is a very compact design that minimizes logic cell count while offering double the bandwidth performance of a 64-bit bus system. An internal write buffer is included in this design to support zero-wait state burst transfer and a very long burst length. The megafunction can transfer data up to 266 Mbytes per second. Both 64-bit and 32-bit data transfer rates are supported by this megafunction. All compliant configuration registers are included in the megafunction and all configuration accesses are processed automatically. The megafunction is available in Intel® Hardware Description Language (HDL), Verilog HDL, VHDL, and netlist format. Megafunction sizes vary with features and customization. Contact Eureka Technology for a logic cell count that is based on user specifications.

Features

  • Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
  • 33-MHz operating frequency
  • Zero-wait state burst data transfer with internal write buffer
  • 64-bit PCI bus

Device Utilization and Performance

1000 LE

Getting Started

N/A

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportAll PCI compatible
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Verification
Simulators supportedVerilog/VHDL
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
Y
If yes, which test(s)?PCI Compliance
If yes, on which Altera device(s)?Flex10K
If Yes, date performed
01/01/1997
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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