32-bit PCI Host Bridge

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The 32 bit PCI host bridge is designed for interfacing the host central processing unit (CPU) with the PCI bus. It contains options to support a 32 bit or 64 bit backend bus for different CPUs. It consists of three functions: bus master, bus target, and configuration access generation. A highly efficient and flexible back-end bus interfaces with the system CPU and user-defined logic such as direct memory access (DMA) and memory controllers. The core utilizes the double data buffer design approach that minimizes design gate count and achieves the highest possible data bandwidth at the same time. It allows the CPU or user logic to initialize the entire system during power-up reset. Configuration Mechanism 1, as defined by the PCI specification, is implemented by the host bridge and supports both type zero and type one transactions. This IP is available in Intel® hardware description language, Verilog, VHDL, and netlist format.


  • Designed for programmable logic device (PLD) and ASIC implementation in various system environments
  • Fully static design with edge-triggered flip-flops
  • 33-MHz operating frequency
  • Efficient back-end interface for different types of user devices
  • Fully supports PCI specification 2.1 and 2.2 protocols

Device Utilization and Performance

1413 LE

Getting Started


IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportAll PCI compatible
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If yes, which test(s)?PCI Compliance
If yes, on which Altera device(s)?Flex10K
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

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