32-bit PCI Host Bridge
Block Diagram
Overview
The 32 bit PCI host bridge is designed for interfacing the host central processing unit (CPU) with the PCI bus. It contains options to support a 32 bit or 64 bit backend bus for different CPUs. It consists of three functions: bus master, bus target, and configuration access generation. A highly efficient and flexible back-end bus interfaces with the system CPU and user-defined logic such as direct memory access (DMA) and memory controllers. The core utilizes the double data buffer design approach that minimizes design gate count and achieves the highest possible data bandwidth at the same time. It allows the CPU or user logic to initialize the entire system during power-up reset. Configuration Mechanism 1, as defined by the PCI specification, is implemented by the host bridge and supports both type zero and type one transactions. This IP is available in Intel® hardware description language, Verilog, VHDL, and netlist format.
Features
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | All PCI compatible |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PCI Compliance |
| If yes, on which Altera device(s)? | Flex10K |
| If Yes, date performed | 01/01/1997 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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