32-Bit PCI Bus Target Interface

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The 32-bit PCI target interface megafunction provides a user-friendly interface between a target device and a PCI bus. This megafunction is a very compact design that minimizes logic cell count while providing a high-bandwidth data transfer. The megafunction performs all data transfer functions requested by the PCI bus master. To maximize data bandwidth, the megafunction provides an internal write buffer and supports burst mode data transfer. All PCI configuration requests are processed locally by the megafunction.

Features

  • Internal write buffer to maximize data bandwidth
  • Efficient back-end interface for different types of user devices
  • Optional first-in first-out (FIFO) interface
  • Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
  • Supports zero-wait state burst mode data transfer

Device Utilization and Performance

1193 LE

Getting Started

For additional information, you can contact Eureka Technology, Inc. at:Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Basic
Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportAll PCI compatible
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Verification
Simulators supportedVerilog/VHDL
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
Y
If yes, which test(s)?PCI Compliance
If yes, on which Altera device(s)?Flex10K
If Yes, date performed
01/01/1997
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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