10G Ultra-low latency TCP/IP + MAC + PCS Ethernet IP Cores
Block Diagram

Overview
nxTCP Financial Edition, 10G Ultra-low latency TCP/IP + MAC + PCS IP Cores for FPGAs The world’s most reliable and mature full hardware ultra-low latency TCP/IP, MAC and PCS IP Cores. Bring the best-in-class ultra-low latency network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.
Features
- Best-in-class ultra-low latency from wire to user’s logic. 10G Ethernet connectivity. Maximum bandwidth delivered.
- Full RTL Layers 1, 2, 3 and 4, which include Enyx proprietary ultra-low latency full hardware TCP/IP, ARP, ICMP, MAC and PCS implementations.
- Clock configurable at up to 250 MHz, for improved latency results.
- Easy to use standardized Avalon and AXI-4 interfaces.
- Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique IPv4, MAC address, VLAN ID, Gateway and Mask.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2015 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Getting Started Guide |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog; VHDL |
Testbench language | Verilog; VHDL |
Software drivers provided | Y |
Driver OS support | OS-independent and Linux |
Implementation | |
User Interface | AXI; Avalon-MM; Other: Avalon-ST |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, Aldec |
Hardware validated | Y. Altera Board Name Altera Stratix V GX FPGA Dev. Kit, BittWare S5-PCIe-HQ, ReFLEX CES Stratix 5 and Arria 10 boards |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | Y |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.