10G Ultra-low latency TCP/IP + MAC + PCS Ethernet IP Cores

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Stratix Series: Stratix® V


nxTCP Financial Edition, 10G Ultra-low latency TCP/IP + MAC + PCS IP Cores for FPGAs The world’s most reliable and mature full hardware ultra-low latency TCP/IP, MAC and PCS IP Cores. Bring the best-in-class ultra-low latency network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.


  • Best-in-class ultra-low latency from wire to user’s logic. 10G Ethernet connectivity. Maximum bandwidth delivered.
  • Full RTL Layers 1, 2, 3 and 4, which include Enyx proprietary ultra-low latency full hardware TCP/IP, ARP, ICMP, MAC and PCS implementations.
  • Clock configurable at up to 250 MHz, for improved latency results.
  • Easy to use standardized Avalon and AXI-4 interfaces.
  • Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique IPv4, MAC address, VLAN ID, Gateway and Mask.

Device Utilization and Performance

Please refer to http://www.enyx.com/nxtcp-financial-edition/

Getting Started

Free 30-day evaluation and full documentation available. Request them at contact@enyx.com

IP Quality Metrics

Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Getting Started Guide
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportOS-independent and Linux
User InterfaceAXI; Avalon-MM; Other: Avalon-ST
IP-XACT Metadata includedN
Simulators supportedModelSim, Aldec
Hardware validated Y. Altera Board Name Altera Stratix V GX FPGA Dev. Kit, BittWare S5-PCIe-HQ, ReFLEX CES Stratix 5 and Arria 10 boards
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  Y

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