nxMAC + nxPCS Financial Edition, 10G Ultra-low latency MAC + PCS IP core for FPGAs
The world’s most reliable and mature full hardware ultra-low latency MAC and PCS IP Cores.
Bring the best-in-class ultra-low latency network connectivity to your hardware code and algorithms with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.
Best-in-class latency from the wire to the user’s own logic. 10G Ethernet connectivity. Maximum bandwidth delivered.
Full RTL Enyx proprietary ultra-low latency hardware MAC and PCS implementations.
Clock configurable at up to 250 MHz, for improved latency results.
Easy to use standardized Avalon and AXI-4 interfaces.
Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique MAC address.
Device Utilization and Performance
Please refer to http://www.enyx.com/nxmac-nxpcs-financial-edition/
Free 30-day evaluation and full documentation available. Request them at email@example.com
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Getting Started Guide
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
OS-independent and Linux
AXI; Avalon-MM; Other: Avalon-ST
IP-XACT Metadata included
Y. Altera Board Name Altera Stratix V GX FPGA Dev. Kit, BittWare S5-PCIe-HQ, ReFLEX CES Stratix 5 and Arria 10 boards
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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