Stream Buffer Controller IP Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Basic Functions: DMA

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Stream Buffer Controller IP Core implements a versatile Stream to Memory Mapped DMA bridge with 16 independent streams. The IP core allows data buffering in an external memory device to provide virtual FIFO capability with up to 4 GByte memory size. It provides AMBA AXI4-Stream interfaces for each write and read data stream. A common memory-mapped master interface (AXI or Avalon) is provided to access the external memory device over an interconnect. The IP core is highly configurable and supports four different operation modes for each channel: •\tFIFO mode: writing and reading to the memory is done over the AXI4-Stream interfaces •\tWrite mode: Writing to the memory is done over the AXI4-Stream, Reading from the memory is done by a CPU. •\tRead mode: Writing to the memory is done by a CPU, reading from the memory is done over the AXI4-Stream interface. •\tROM mode: Reading from the memory is done over the AXI4-Stream interface. The memory must be initially written by a CPU

Features

  • Data width conversion to/from any byte-multiple width
  • Supports up to 16 write and read streams (depending on product options)
  • Configurable status flags for write and read path
  • Available with Avalon or AMBA-AXI interface

Device Utilization and Performance

Depends heavily on configuration. Details on request.

Getting Started

Enclustra offers a free evaluation license with a reference design and an evaluation kit to get started.

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported17.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportDriverless
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim PE
Hardware validated Y. Altera Board Name Mercury CA1 / Mercury SA1 & Mercury+PE1
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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