FPGA Manager Ethernet IP Solution

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC


Enclustra’s FPGA Manager solution allows for easy and efficient data transfer between a host and a FPGA over different interface standards like USB 2.0/3.0, Gigabit Ethernet and PCI Express. The solution includes a host software library (DLL), a suitable IP core for the FPGA and device controller firmware, if necessary. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. Both streaming and memory-mapped access are supported. The FPGA Manager IP Solution Supports C, C++, C# and MATLAB user applications and Windows and Linux as operation systems.


  • Complete and easy to use solution for communication between FPGA and host
  • No need for dealing with complexity of underlying protocols
  • Streaming data transfer between FPGA and host, Memory-mapped access to FPGA AXI bus
  • Same API for Ethernet, USB and PCIe communication
  • No Royalties

Device Utilization and Performance

Gigabit Ethernet: up to 123 MB/s USB 3.0: up to 188 MB/s (Currently limited by 16 bit wide interface to Cypress FX3 USB 3.0 peripheral controller) PCIe: up to 777 MB/s (PCIe gen 1 x4)

Getting Started

Enclustra offers a free evaluation license with a reference design to get started. Also training or workshops are available.

IP Quality Metrics

Year IP was first released2012
Latest version of Quartus supported17.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportWindows 7, Linux
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim PE
Hardware validated N. Altera Board Name Enclustra Mercury SA1 & Mercury+ PE1
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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