FPGA Manager Ethernet IP Solution
Block Diagram

Overview
Enclustra’s FPGA Manager solution allows for easy and efficient data transfer between a host and a FPGA over different interface standards like USB 2.0/3.0, Gigabit Ethernet and PCI Express. The solution includes a host software library (DLL), a suitable IP core for the FPGA and device controller firmware, if necessary. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. Both streaming and memory-mapped access are supported. The FPGA Manager IP Solution Supports C, C++, C# and MATLAB user applications and Windows and Linux as operation systems.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 17.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | Y |
Driver OS support | Windows 7, Linux |
Implementation | |
User Interface | AXI; Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim PE |
Hardware validated | N. Altera Board Name Enclustra Mercury SA1 & Mercury+ PE1 |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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