Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Stratix® IV, Stratix® V
The Display Controller IP Core enables the easy addition of a display to existing or future FPGA designs, allowing the system designer to focus on the main application instead of dealing with display control issues. In addition, there is no need for an external display controller device that would consume precious PCB space and unnecessarily extend the project's BOM.With its modular design and strong scalability, the Display Controller IP Core perfectly fits the system requirements without wasting any FPGA resources. These unique features will also simplify the reuse of the Display Controller IP Core in future projects. Selecting our Display Controller IP Core for the display control needs of present or future projects will significantly reduce time to market as well as the overall system cost.
Support for parallel, LVDS and HDMI/DVI displays without external display controller device
Support for unlimited video pages
Built-in PWM generator for display brightness control
Optional 2D accelerator unit (draw/copy rectangles, supports transparent color)
Supported color modes: 16-bit true color (5/6/5) and 24-bit true color
Enclustra offers a free evaluation license with a reference design including a NIOS® II to get started.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Enclustra Mercury SA1 & Mercury+ PE1
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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