SD/MMC SPI Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Memory Interfaces and Controllers

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The SD/MMC SPI core with Intel® FPGA Avalon bus interface allows the designer to easily connect Platform Designer(formerly Qsys) systems to standard MMC and SD card flash-based memory devices. The MMC and SD cards are universal, low-cost data storage and communication media widely used in consumer products such as digital cameras and cellular phones. The SD/MMC SPI core is fully compliant with Platform Designer and integrates easily into any such system. For the Nios® II processor, El Camino provides low-level driver routines for the SD/MMC SPI core. The drivers provide universal access routines for MMC and SD memory devices, eliminating the need for additional low-level code to read or write raw data from or to the SD/MMC cards.

Features

  • Optional Stand-Alone FAT12/16/32 file system support
  • More than 2400 kByte/s read and 2400 kByte/s write performance
  • Low-level drivers included and automatically integrated into NIOS® HAL
  • Hardware assisted CRC calculation
  • Supports MultiMediaCard (MMC) and Secure Digital Card (SD, SDHC, SDXC) in SPI mode

Device Utilization and Performance

Depending on the target device family the IP core requires approximately 320 Logic Elements and supports system clocks around 180 MHz.

Getting Started

Contact El Camino to receive a free evaluation version of the core. This comes with a Platform Designer based example design that can easily be adapted to any standard prototyping kit or custom hardware platform. Furthermore we provide two software examples, one for low level FLASH like access as well as one for high level FAT12/16/32 file I/O.

IP Quality Metrics

Basic
Year IP was first released2005
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportNios HAL
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Nios Embedded Evaluation Kit (NEEK) and others
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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