From El Camino GmbH

SD Bus Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

The SD BUS Core with Avalon Interface allows for Qsys systems to access standard SD, MMC or eMMC flash based memory devices. It comes with low-level SD Card driver routines for Nios® II and is integrated into the HAL generic device model classes as a FLASH memory device. Therefore you do not need to write any additional low level code to read or write raw data from or to SD cards.El Camino offers an optional stand-alone FAT12/16/32 file system that can be used to read or write files on SD cards from a NIOS system.Furhtermore the core is implemented such that it works with the standard sdhci/sdhci-pltfm Linux drivers e.g. on Intel® SoC FPGA devices.

Features

Supports Secure Digital Card (SD, SDHC, SDXC), Multimedia Card (MMC) and embedded Multimedia Card (eMMC)
1 bit and 4 bit (wide bus) operation
Compatible with SD Host Controller Standard Specification V3.01
Supports High Speed Mode (SDHS) with up to 50 MHz SD Clock rate
Low-level Nios® II drivers included and compatible with Linux sdhci/sdhci-pltfm drivers

Device Utilization and Performance

Depending on the target device family the IP core requires approximately 850 ALMs and supports system clocks around 200 MHz.

Getting Started

Contact El Camino to receive a free evaluation version of the core. This comes with two Qsys/Platform Designer based example designs for Nios II and Intel SoC FPGA that can easily be adapted to any standard prototyping kit or custom hardware platform. Furthermore we provide software examples, for low level FLASH like access as well as high level FAT12/16/32 file I/O.

IP Quality Metrics

Basic
Year IP was first released	2008
Latest version of Quartus supported	18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	Y
Driver OS support	NIOS HAL, Linux
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim
Hardware validated	Y. Altera Board Name Nios Embedded Evaluation Kit (NEEK), Cyclone V SoC Kit
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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