DTPCI32DC - Dual Clock 32bit PCI Bus Target Interface

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Overview

The DTPCI32DC is a 32-bit target interface which provides all requirements of the PCI 3.0 specification for a target device. It compromises a minimal gate count with a high-bandwidth data transfer. Core’s main feature is the presence of two clock domains. They enable flexibility and higher performance as well. When time required for implementation becomes crucial, the DTPCI32DC brings domain crossing. Saved time can be used for a specific system implementation instead. The user-friendly back-end interface can be very easily and effectively tailored to the design needs. The Core supports up to six Base Address Registers and Expansion Rom address register with both I/O and Memory space decoding from 16 bytes up to 4 GB. Another important feature is a cache wrapping hardware support and cacheline pre-fetching capability. The DTPCI32DC is accepting size cache lines which are powered from 2 up to 128. It enables also target-disconnect with data, without data or by a target abort.

Features

  • Fully supports PCI specification 3.0 protocol
  • Stable clock domain crossing regardless of the clock frequencies
  • Cache wrapping (cache lines must be powers of 2)
  • User controlled burst data transfer
  • Possible no-wait state transactions

Device Utilization and Performance

Sample utilization and performance results for Cyclone V are as follows: LE/ALM: 507/359 | Memory Bits: 256 | Fmax: 183 MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  Y

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