DSPIS - Serial Peripheral Interface Slave

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The DSPIS is a fully configurable SPI slave device, designated to operate with passive devices, like memories, LCD drivers etc. It allows you to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes information shifting and sampling on the two independent serial data lines. Moreover, the data is simultaneously transmitted and received. The DSPIS system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The clock control logic (CLK/4) allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. The DSPIS allows the SPI Master to communicate with passive devices.

Features

  • Full duplex synchronous serial data transfer; Slave operation; Automatic read and write operations
  • Automatic address incrementation after any data portion transfer; Configurable address and data length
  • Configurable SCK phase and polarity; Supports speeds up 1/4 of system clock
  • Simple interface allows easy connection to passive devices and SPI Master; Four transfer formats supported
  • Simple interface allows easy connection to microcontrollers; Fully synthesizable; Static synchronous design

Device Utilization and Performance

Information provided in the product datasheet.

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released2003
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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