Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
The DSPI_FIFO is a fully configurable SPI master/slave device, which allows you to configure polarity and phase of a serial clock signal SCK. It allows a microcontroller to communicate with serial peripheral devices, but also to communicate with an interprocessor in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines.
The DSPI_FIFO data is simultaneously transmitted and received. What's more important, this is a technology independent design, that can be easily implemented in a variety of process technologies. The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4.
SPI Master; SPI Slave; SPI Slave; Two DMA Modes allows single and multi-transfer
In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
Optional FIFO size extension to 128, 256 or 512 Bytes; Available system interface wrappers: AMBA - APB Bus, Altera Avalon Bus, Xilinx OPB Bus
Static synchronous design; Positive edge clocking and no internal tri-states; Scan test ready
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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