DSPI_FIFO - Serial Peripheral Interface Master/Slave with FIFO

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The DSPI_FIFO is a fully configurable SPI master/slave device, which allows you to configure polarity and phase of a serial clock signal SCK. It allows a microcontroller to communicate with serial peripheral devices, but also to communicate with an interprocessor in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines. The DSPI_FIFO data is simultaneously transmitted and received. What's more important, this is a technology independent design, that can be easily implemented in a variety of process technologies. The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4.

Features

  • SPI Master; SPI Slave; SPI Slave; Two DMA Modes allows single and multi-transfer
  • In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
  • Optional FIFO size extension to 128, 256 or 512 Bytes; Available system interface wrappers: AMBA - APB Bus, Altera Avalon Bus, Xilinx OPB Bus
  • Static synchronous design; Positive edge clocking and no internal tri-states; Scan test ready

Device Utilization and Performance

Provided in the product datasheet

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released2004
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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