DMAC-RMII - 10/100 Mb Media Access Controller with RMII

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: MAX® V

Stratix Series: Stratix® IV, Stratix® V


Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC-RMII provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.


  • Conforms to IEEE 802.3-2002 specification; Configurable width CPU interface with little or big endianess: 8-bit, 16-bit and 32-bit
  • Simple interface allows easy connection to CPU; Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
  • Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories; CRC-32 algorithm
  • Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs; Programmable MAC address
  • Dynamic PHY configuration by STA management interface; Programmable MAC address

Device Utilization and Performance

Sample utilization and performance results for Stratix IV are as follows: Speed Grade: -1 | LE/ALM: 896 + 4kb RAM | Memory Bits: 256 | clk/rmiiclk: 420/350 For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: | +48 32 2828266 |

IP Quality Metrics

Year IP was first released2004
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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