DMAC-RMII - 10/100 Mb Media Access Controller with RMII
Block Diagram
Overview
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC-RMII provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.
Features
- Conforms to IEEE 802.3-2002 specification; Configurable width CPU interface with little or big endianess: 8-bit, 16-bit and 32-bit
- Simple interface allows easy connection to CPU; Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
- Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories; CRC-32 algorithm
- Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs; Programmable MAC address
- Dynamic PHY configuration by STA management interface; Programmable MAC address
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2004 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | TBD |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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