From Digital Core Design

DLIN - LIN Bus Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD's controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2.

Features

Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification; Automatic LIN Header handling; Automatic Re-synchronization
Data rate between 1Kbit/s and 20 Kbit/s; Master and Slave work mode; Time-out detection
Break-in-data support; Extended error detection

Device Utilization and Performance

Provided in the product datasheet

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released	2008
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	TBD
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog; VHDL
Testbench language	Verilog; VHDL
Software drivers provided	Y
Driver OS support	TBD
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim
Hardware validated	Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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