DI2CSB - I2C Bus Interface Slave -Base version
Block Diagram
Overview
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can work as a slave receiver or as a transmitter - depending on the working mode determined by the master device. A very simple interface, composed with read, write and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by the I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast, Fast Plus and High Speed.
Features
- Conforms to the latest I2C specification; Slave operation (Slave transmitter, Slave receiver); No programming required
- Supports all transmission speed modes (Standard (up to 100 kb/s); Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s), High Speed (up to 3,4 Mb/s)
- Allows operation from a wide range of input clock frequencies; Support for reads, writes, burst reads, burst writes, and repeated start
- 7-bit addressing; Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
- Fully synthesizable; Static synchronous design; Positive edge clocking and no internal tri-states; Scan test ready
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2001 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | TBD |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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