DI2CS - I2C Bus Interface - Slave

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: MAX® V

Stratix Series: Stratix® IV, Stratix® V


The DI2CS core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as: - a slave transmitter or - slave receiver depending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification including - clock synchronization, - arbitration, - high-speed transmission mode. The DI2CS supports all transmission speed modes: - Standard (up to 100 kb/s) - Fast (up to 400 kb/s) - Fast Plus (up to 1 Mb/s) - High Speed (up to 3,4 Mb/s) DCD's IP Core is a technology independent design which can be implemented in a variety of process technologies.


  • Conforms to v.3.0 of the I2C specification; Slave operation (Slave transmitter, Slave receiver); Interrupt generation
  • Supports all transmission speed modes (Standard (up to 100 kb/s), Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s), High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies; User-defined data setup time
  • Simple interface allows easy connection to microprocessor/microcontroller devices; Fully synthesizable; Static synchronous design
  • Positive edge clocking and no internal tri-states; Scan test ready

Device Utilization and Performance

Sample utilization and performance results for Cyclone are as follows: Speed grade: -6 | LE/ALM: 170 | Fmax: 220 MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Year IP was first released2001
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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