DI2CMS - I2C Bus Interface - Master/Slave

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: MAX® V

Stratix Series: Stratix® IV, Stratix® V

Overview

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and a high-speed transmission mode (the DI2CMS supports all the transmission speed modes). Built-in timer allows operation from a wide range of the clk frequencies. The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs.The DI2CMS is delivered with fully automated testbench and complete set of tests

Features

  • Conforms to v.3.0 of the I2C specification; Master and Slave mode; User-defined timing (data setup, start setup, start hold, etc.)
  • Simple interface allows easy connection to microprocessor/microcontroller devices; Interrupt generation
  • Fully synthesizable; Static synchronous design; Positive edge clocking and no internal tri-states
  • Scan test ready

Device Utilization and Performance

Sample utilization and performance results for Cyclone V are as follows: Speed grade: -6 | LE/ALM: 354 | Fmax: 263 MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Basic
Year IP was first released2000
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.