DI2CM - I2C Bus Interface - Master

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Overview

The DI2CM core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as: - a master transmitter or - master receiver depending on a working mode determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM is a technology independent design that can be implemented in variety of process technologies.

Features

  • Conforms to v.3.0 of the I2C specification; Master operation (Master transmitter, Master receiver); Arbitration and clock synchronization
  • Support for all transmission speeds (Standard (up to 100 kb/s), Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s), High Speed (up to 3,4 Mb/s)
  • Support for multi-master systems; Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Interrupt generation; Build-in 8-bit timer for data transfers speed adjusting; User-defined timing (data setup, start setup, start hold, etc.)
  • Host side interface dedicated for microprocessors/microcontrollers; Fully synthesizable; Static synchronous design; Scan test ready

Device Utilization and Performance

Sample utilization and performance results for Stratix IV are as follows: LE/ALM: 205 | Fmax: 430 MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Basic
Year IP was first released2000
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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