DI2CM - I2C Bus Interface - Master
Block Diagram
Overview
The DI2CM core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as: - a master transmitter or - master receiver depending on a working mode determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM is a technology independent design that can be implemented in variety of process technologies.
Features
- Conforms to v.3.0 of the I2C specification; Master operation (Master transmitter, Master receiver); Arbitration and clock synchronization
- Support for all transmission speeds (Standard (up to 100 kb/s), Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s), High Speed (up to 3,4 Mb/s)
- Support for multi-master systems; Support for both 7-bit and 10-bit addressing formats on the I2C bus
- Interrupt generation; Build-in 8-bit timer for data transfers speed adjusting; User-defined timing (data setup, start setup, start hold, etc.)
- Host side interface dedicated for microprocessors/microcontrollers; Fully synthesizable; Static synchronous design; Scan test ready
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2000 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | TBD |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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