Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
The I2C is a two-wire, bi-directional serial bus, which provides simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface between a microprocessor/microcontroller and the I2C bus. It can work as a master transmitter or a master receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and high-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CM is a technology independent design, that can be implemented in a variety of process technologies.
Conforms to v.3.0 of the I2C specification; Master operation (Master transmitter, Master receiver); Arbitration and clock synchronization
Support for all transmission speeds (Standard (up to 100 kb/s), Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s), High Speed (up to 3,4 Mb/s)
Support for multi-master systems; Support for both 7-bit and 10-bit addressing formats on the I2C bus
Interrupt generation; Build-in 8-bit timer for data transfers speed adjusting; User-defined timing (data setup, start setup, start hold, etc.)
Host side interface dedicated for microprocessors/microcontrollers; Fully synthesizable; Static synchronous design; Scan test ready
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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