DHDLC HDLC/SDLC controller
Block Diagram

Overview
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, no matter if it's 8-, 16- or 32-bit microcontroller. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter.
Features
- Two separate receiver and transmitter interfaces; Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing; Address recognition for receiver and address insertion for transmitter; ##Two or one byte address field
- CRC-16 and CRC-32 computation and checking; Collision detection; Byte alignment error detection
- Programmable number of bits for idle detection; NRZI coding support; Shared flags, shared zeroes support
- Pad fill with flags option; Transmitter clock generation; 8-bit, 16-bit, 32-bit CPU interface
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2013 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | TBD |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog; VHDL |
Testbench language | Verilog; VHDL |
Software drivers provided | Y |
Driver OS support | TBD |
Implementation | |
User Interface | AXI; Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim |
Hardware validated | Y. Altera Board Name DE1, DE2 |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | Y |
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