DFPAU - Floating-Point Arithmetic Unit

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The DFPAU is a Floating Point Arithmetic Coproces-sor, designed to assist the CPU in performing float-ing point arithmetic computations. The DFPAU replaces directly C software functions, by equiva-lent, very fast hardware operations, which signifi-cantly accelerate system performance. It doesn't require any programming, so it also doesn't re-quire any modifications to be made in the main software. Everything is done automatically during software compilation, by the DFPAU C driver. The DFPAU was designed to operate with DCD's DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPAU package. The DFPAU uses specialized algorithms to compute arithmetic functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value and change sign of a number. The input numbers format is in accordance with the IEEE-754 standard single precision real numbers.


  • Direct replacement for C float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
  • C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
  • No programming required
  • IEEE-754 Single precision real format support float type
  • Flexible arguments and result registers location

Device Utilization and Performance

Provided in the product datasheet

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Year IP was first released2002
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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