DCAN FD - Configurable CAN Bus Controller with Flexible Data-Rate
Block Diagram
Overview
The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. The DCAN FD has been designed in accordance to ISO 11898-1:2015. It conforms to: - Bosch CAN 2.0B specification (2.0B Active) and - CAN FD (flexible data-rate). Sophisticated error detection functions, which increase communication reliability and unique fault confinement, what guarantees network-wide data consistency have decided about CAN’s popularity. Because of its fundamental role in all aspects of security and safety, trustworthy implementations are crucial. That’s why Digital Core Design developed unique IP Core, which delimits the highest quality standards. The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the payload (data field) is up to 64 byte long and limited to 8 byte anymore. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized.
Features
- Designed in accordance to ISO 11898-1:2015; Supports CAN 2.0B and CAN FD frames; Support up to 64 bytes data frames
- Flexible data-rates supported; 8/16/32-bit CPU slave interface with small or big endianness; Simple interface allows easy connection to CPU
- Supports both standard (11-bit identifier) and extended (29 bit identifier) frames; Data rate up to 8 Mbps; Hardware message filtering
- 128 byte receive FIFO and transmit buffer; Overload frame is generated on FIFO overflow; Normal & Listen Only Mode;
- Single Shot transmission; Ability to abort transmission; Readable error counters; Last Error Code; Fully synthesizable
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | TBD |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | Y |
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