Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
The DCD’s DBLCD32 core is a fully configurable, universal LCD/TFT display controller. It supports a wide range of resolution and enables both, horizontal and vertical synchronization parameters setup. The display’s pixel clock can be generated by an internal pixel clock divider based on the bus clock, or delivered to the core by a dedicated pin. Additionally there is a possibility of using an externally generated pixel clock. Polarization of the generated pixel clock, as well as synchronization signals, is configurable. The DBLCD32 has a DMA capable master interface, which can be used to access a framebuffer placed directly in a system memory. Embedded DMA controller has configurable FIFO to store pixels data, which increases system throughput and performance. Transmission on the master interface is burst oriented and there is a possibility of defining the burst size limit. Data fetched by the DMA interface can be translated to 24-bits RGB signals, depending on the selected color mode.
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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