D8255 - Programmable Peripheral Interface

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The D8255 is a programmable I/O device designed to be used with all Intel CPUs. What's significant, it also supports most other microprocessors. Our onnovative IP core provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation: - Mode 0 - Basic Input/Output. - MODE 1 - Strobed Input/Output - MODE 2 - Strobed Bidirectional Bus I/O The functional configuration of the D8255 is programmed by the system software, so that normally no external logic is needed to interface peripheral devices or structures.

Features

  • Compatible with industry standard 8255; 24 I/O lines individually programmed in 2 groups of 12
  • 3 major modes of operation; Control Word Read-Back Capability; Direct Bit Set/Reset Capability
  • Interrupt control functions; No internal three states busses; Fully synthesizable, technology independent source code

Device Utilization and Performance

Sample utilization and performance results for Stratix II are as follows: Speed Grade: -5 | Fmax: 179 MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Basic
Year IP was first released2006
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  Y

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