D6840 - Programmable Timer Module
Block Diagram
Overview
The D6840 is a programmable timer module, compatible with the 6840 industry standard. It was designed to be used in a peripheral device for D68xx processors. Moreover, our proprietary IP Core works perfectly as a separate module in applications, where 6840 timer features are useful. The D6840 has three separate 16-bit timers, with individual control and common status registers. The timers may be used for square wave generation with duty cycle regulation. The signal may then be generated as a continuous wave or a single-shot mode. But this is not all - our unique module can be used for frequency or pulse width measurement and comparison. The D6840 has an interrupt, which is useful in a controlling module by the CPU. As all of our solutions, the D6840 is a technology independent design, that can be implemented in a variety of process technologies.
Features
- Compatible with the 6840 industry standard; Three separate timers; Two operation modes (Wave synthesis and Wave measurement)
- Two generation modes (Continuous and Single shot); Gating system for each clock input; Separate timer outputs
- Prescaler mode for timer3 input clock; External clock or E clock used for timer decrement; Interrupt generation
- Split bus for input and output data; Fully synthesizable; Static synchronous design and no internal tri-states
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2006 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | NA |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | Y |
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