From Digital Core Design

D16750 - Configurable UART with FIFO and hardware flow control

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The D16750 is a soft Core of a Universal Asynchronous Receiver / Transmitter (UART), functionally identical to the TL16C750. The D16750 allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing up to 512 bytes (plus 3 bits data error per byte in the RCVR FIFO) to be stored, both in receive and transmit directions. Our trustworthy core performs serial-to-parallel conversion on data characters, received from a peripheral device or from a MODEM, and a parallel-to-serial conversion on data characters, received from the CPU. The CPU can read acomplete status of the UART at any time, during the functional operation. The reported status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt).

Features

Software compatible with 16450, 16550, and 16750 UARTs; Configuration capability; Separate configurable BAUD clock line
Majority Voting Logic; Supports RS232 and RS485 standards; Two modes of operation: UART mode and FIFO mode
Configurable FIFO size allowing up to 512 levels deep FIFOs in both Rx and Tx directions
Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
Independently controlled transmit, receive, line status and data set interrupts; False start bit detection

Device Utilization and Performance

Provided in the product datasheet.

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released	2003
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog; VHDL
Testbench language	Verilog; VHDL
Software drivers provided	Y
Driver OS support	TBD
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim
Hardware validated	Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	Y

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